Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Product-shuffle networks: toward reconciling shuffles and butterflies
Discrete Applied Mathematics - Special double volume: interconnection networks
Mesh-Connected Trees: A Bridge Between Grids and Meshes of Trees
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
The Hyper-deBruijn Networks: Scalable Versatile Architecture
IEEE Transactions on Parallel and Distributed Systems
Products of Networks with Logarithmic Diameter and Fixed Degree
IEEE Transactions on Parallel and Distributed Systems
On the Crossing Number of the Hypercube and the Cube Connected Cycles
WG '91 Proceedings of the 17th International Workshop
A complexity theory for VLSI
Area-efficient vlsi computation
Area-efficient vlsi computation
Computational Aspects of VLSI
VLSI layout and packaging of butterfly networks
Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures
Generalized Algorithm for Parallel Sorting on Product Networks
IEEE Transactions on Parallel and Distributed Systems
Constructing Edge-Disjoint Spanning Trees in Product Networks
IEEE Transactions on Parallel and Distributed Systems
Multilayer VLSI Layout for Interconnection Networks
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
A generalized fault-tolerant sorting algorithm on a product network
Journal of Systems Architecture: the EUROMICRO Journal
The necklace-hypercube: a well scalable hypercube-based interconnection network for multiprocessors
Proceedings of the 2005 ACM symposium on Applied computing
Capturing an intruder in product networks
Journal of Parallel and Distributed Computing
Efficient preprocessing for VLSI optimization problems
Computational Optimization and Applications
Resource placement in Cartesian product of networks
Journal of Parallel and Distributed Computing
Capturing an intruder in product networks
HiPC'06 Proceedings of the 13th international conference on High Performance Computing
Volumes of 3d drawings of homogenous product graphs
SOFSEM'05 Proceedings of the 31st international conference on Theory and Practice of Computer Science
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In this paper, we develop generalized methods to layout homogeneous product networks with any number of dimensions, and analyze their VLSI complexity by deriving upper and lower bounds on the area and maximum wire length.In the literature, lower bounds are generally obtained by computing lower bounds on the bisection width or the crossing number of the network being laid out. In this paper, we define a new measure that we call "maximal congestion," that can be used to obtain both the bisection width and the crossing number, thereby unifying the two approaches. Upper bounds are traditionally obtained by constructing layouts based on separators or bifurcators. Both methods have the basic limitation that they are applicable only for graphs with bounded vertex degree. The separators approach generally yields good layouts when good separators can be found, but it is difficult to find a good separator for an arbitrary graph. The bifurcators approach is easier to apply, but it generally yields larger area and wire lengths. We show how to obtain "strong separators" as well as bifurcators for any homogeneous product network, as long as the factor graph has bounded vertex degree. We illustrate application of both methods to layout a number of interesting product networks.Furthermore, we introduce a new layout method for product networks based on the combination of collinear layouts. This method is more powerful than the two methods above because it is applicable even when the factor graph has unbounded vertex degree. It also yields smaller area than the earlier methods. In fact, our method has led to the optimal area for all of the homogeneous product networks we considered in this paper with one exception, which is very close to optimal. In regards to wire lengths, the results obtained by our method turned out to be the best of the three methods for all the examples we considered, again subject to one (and the same) exception. We give an extensive variety of such examples.