The Cross Product of Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
Efficient VLSI Layouts for Homogeneous Product Networks
IEEE Transactions on Computers
The hyperstar interconnection network
Journal of Parallel and Distributed Computing
Macro-Star Networks: Efficient Low-Degree Alternatives to Star Graphs
IEEE Transactions on Parallel and Distributed Systems
Journal of Systems Architecture: the EUROMICRO Journal
Area-Efficient VLSI Layouts for Binary Hypercubes
IEEE Transactions on Computers
Topological Properties of OTIS-Networks
IEEE Transactions on Parallel and Distributed Systems
Products of Networks with Logarithmic Diameter and Fixed Degree
IEEE Transactions on Parallel and Distributed Systems
Efficient VLSI Layouts of Hypercubic Networks
FRONTIERS '99 Proceedings of the The 7th Symposium on the Frontiers of Massively Parallel Computation
On Some Properties of k-Ary n-Cubes
ICPADS '01 Proceedings of the Eighth International Conference on Parallel and Distributed Systems
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In this paper, we introduce a new interconnection network, namely the necklace-hypercube, based on the binary cube with an array of processors (as a necklace of processors) attached to each two adjacent nodes of the hypercube network. Topological properties of the proposed network are studied. Some important basic operations such as optimal routing and VLSI layout in necklace-hypercubes are also addressed here. Moreover, a comparison between the necklace-hypercube and some other popular networks is conducted. The comparison is based on VLSI layout, scalability, and other static topological properties. Area-efficient VLSI layout and network scalability of the necklace-hypercube make it an attractive alternative to the well-known hypercube network topology, while keeping most of desirable properties of the hypercube.