Implementation of Data Manipulating Functions on the STARAN Associative Processor
Proceedings of the Sagamore Computer Conference on Parallel Processing
MIMD machine communication using the augmented data manipulator network
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
An emulator network for SIMD machine interconnection networks
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Study of multistage SIMD interconnection networks
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
A large scale, homogeneous, fully distributed parallel machine, I
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Microprocessor implementation of a parallel processor
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
Data Manipulating Functions in Parallel Processors and Their Implementations
IEEE Transactions on Computers
The Indirect Binary n-Cube Microprocessor Array
IEEE Transactions on Computers
Resource Optimization of a Parallel Computer for Multiple Vector Processing
IEEE Transactions on Computers
Implementation of Permutation Functions in Illiac IV-Type Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
A Model of SIMD Machines and a Comparison of Various Interconnection Networks
IEEE Transactions on Computers
A Shuffle-Exchange Network with Simplified Control
IEEE Transactions on Computers
An efficient routing control for the SIGMA network Σ(4)
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Partitionability of the Multistage Interconnection Networks
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
A state-of-the-art SIMD two-dimensional FFT array processor
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
On the Number of Permutations Performable by the Augmented Data Manipulator Network
IEEE Transactions on Computers
Supersystems: Technology and Architecture
IEEE Transactions on Computers
The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems
IEEE Transactions on Computers
High-Speed Multiprocessors and Compilation Techniques
IEEE Transactions on Computers
Resource Optimization of a Parallel Computer for Multiple Vector Processing
IEEE Transactions on Computers
IEEE Transactions on Computers
Routing Schemes for the Augmented Data Manipulator Network in an MIMD System
IEEE Transactions on Computers
PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition
IEEE Transactions on Computers
Shuffling with the Illiac and PM2I SIMD Networks
IEEE Transactions on Computers
| Hi-index | 15.01 |
The age of the microcomputer has made feasible large-scale multiprocessor systems. In order to use this parallel processing power in the form of a flexible multiple-SIMD (MSIMD) system, the interconnection network must be partitionable and dynamically reconfigurable. The theory underlying the partitioning of MSIMD system permutation networks into independent subnetworks is explored. Conditions for determining if a network can be partitioned into independent subnetworks and the ways in which it can be partitioned are presented. The use of the theory is demonstrated by applying it to the Cube, Illiac, PM2I, and Shuffle-Exchange SIMD machine interconnection networks. Both recirculating (single stage) and multistage network implementations are considered.