Implementation of Data Manipulating Functions on the STARAN Associative Processor
Proceedings of the Sagamore Computer Conference on Parallel Processing
Programmable Radar Signal Processing Using the Rap
Proceedings of the Sagamore Computer Conference on Parallel Processing
Study of multistage SIMD interconnection networks
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
The universality of various types of SIMD machine interconnection networks
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Classification Categories and Historical Development of Circuit Switching Topologies
ACM Computing Surveys (CSUR)
MIMD machine communication using the augmented data manipulator network
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
The Theory Underlying the Partitioning of Permutation Networks
IEEE Transactions on Computers
A customized cross-bar for data-shuffling in domain-specific simd processors
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
Journal of Systems Architecture: the EUROMICRO Journal
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The emulator network, a single stage interconnection network, can be used to simulate a wide variety of single stage and multistage SIMD interconnection networks. These include the STARAN, the omega, the data manipulator, and the Illiac networks. A hardware design for the emulator network is presented. It is shown how the emulator network can be used to test different network control schemes. Its performance in a partitioned machine environment is discussed. It is well suited for use in SIMD system prototypes being built to study the effectiveness of various design parameters.