Determining an Optimal Secondary Storage Service Rate for the PASM Control System
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Permutations on Illiac IV-Type Networks
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Optimal Graph Algorithms on a Fixed-Size Linear Array
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The Computation of Window Operations on a Parallel Organized Computer A Case Study
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Optimal Sorting Algorithms for Parallel Computers
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Parallel Processing with the Perfect Shuffle
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Two-Dimensional Microprocessor Pipelines for Image Processing
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Data Manipulating Functions in Parallel Processors and Their Implementations
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Communication Structures for Large Networks of Microcomputers
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Analysis of Chordal Ring Network
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CONET: A Connection Network Model
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Interconnections Between Processors and Memory Modules Using the Shuffle-Exchange Network
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The Piecewise Data Flow Architecture: Architectural Concepts
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Technology and Design Tradeoffs in the Creation of a Modern Supercomputer
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The Burroughs Scientific Processor (BSP)
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Supersystems: Technology and Architecture
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The Indirect Binary n-Cube Microprocessor Array
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Performance-Related Reliability Measures for Computing Systems
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Parallel Permutations of Data: A Benes Network Control Algorithm for Frequently Used Permutations
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The ILLIAC IV Processing Element
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A Uniform Representation of Single-and Multistage Interconnection Networks Used in SIMD Machines
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The Theory Underlying the Partitioning of Permutation Networks
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Resource Optimization of a Parallel Computer for Multiple Vector Processing
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Implementation of Permutation Functions in Illiac IV-Type Computers
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The Expression Processor: A Pipelined, Multiple- Processor Architecture
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A Preprocessing High-Speed Memory System
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Performance of a Simulated Dataflow Computer
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PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition
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Real-Time Algorithms and Data Management on Illiac IV
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| Hi-index | 15.10 |
Abstract The structure of ILLIAC IV, a parallel-array computer containing 256 processing elements, is described. Special features include multiarray processing, multiprecision arithmetic, and fast data-routing interconnections. Individual processing elements execute 4脳106 instructions per second to yield an effective rate of 109 operations per second.