ACM Computing Surveys (CSUR)
A Survey of Parallel Machine Organization and Programming
ACM Computing Surveys (CSUR)
ACM Computing Surveys (CSUR)
Structure of Computers and Computations
Structure of Computers and Computations
First version of a data flow procedure language
Programming Symposium, Proceedings Colloque sur la Programmation
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
IEEE Transactions on Computers
The Inhibition of Potential Parallelism by Conditional Jumps
IEEE Transactions on Computers
Design of a Functionally Distributed, Multiprocessor Database Machine Using Data Flow Analysis
IEEE Transactions on Computers
The Piecewise Data Flow Architecture: Architectural Concepts
IEEE Transactions on Computers
Bit-Sequential Arithmetic for Parallel Processors
IEEE Transactions on Computers
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A nem multiple-processor architecture is described that can exploit the instruction level concurrency in numerical processing tasks. The expression processor contains multiple processing elements (PE's), which can be configured either as an SIMD [8] array or as an expression tree pipeline. An expression tree is the parse tree conctructed by a compiler from an arithmetic or logical expression. The expression tree pipeline, or "X-Pipe," is a binary-tree networks of PE'S upon which expression tress are executed intact.A series of expression trees can be executed in pipelined fashion for enhanced concurrency. With this capability, the expression processor can exploit the concurrency in vector merges and scalar tasks, as well as conventional vector tasks. The architecture is designed for low-cost implementation using large-scale in (LSI) components.