An Adaptation of the Fast Fourier Transform for Parallel Processing
Journal of the ACM (JACM)
Computer Organization and Architecture
Computer Organization and Architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
Data Manipulating Functions in Parallel Processors and Their Implementations
IEEE Transactions on Computers
Interconnections Between Processors and Memory Modules Using the Shuffle-Exchange Network
IEEE Transactions on Computers
The Indirect Binary n-Cube Microprocessor Array
IEEE Transactions on Computers
IEEE Transactions on Computers
Interconnections for Parallel Memories to Unscramble p-Ordered Vectors
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
A Shuffle-Exchange Network with Simplified Control
IEEE Transactions on Computers
Finite State Model and Compatibility Theory: New Analysis Tools for Permutation Networks
IEEE Transactions on Computers
Permutations on Illiac IV-Type Networks
IEEE Transactions on Computers
Packet Switching Networks for Multiprocessors and Data Flow Computers
IEEE Transactions on Computers
Design and Performance of Generalized Interconnection Networks
IEEE Transactions on Computers
Shuffling with the Illiac and PM2I SIMD Networks
IEEE Transactions on Computers
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A switching theoretic framework for the study of interconnection networks is developed. An equivalence relationship between networks is defined. Single-stage and multistage networks that are particularly useful for single-instruction multiple-data stream (SIMD) machines are studied. It is shown that the networks form two distinct equivalence classes under this definition of equivalence relationship. It is shown that any multistage network can be easily modified to realize the permutations that are admissible by any other network which is equivalent to it.