An Adaptation of the Fast Fourier Transform for Parallel Processing
Journal of the ACM (JACM)
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
Dynamic Memories with Rapid Random and Sequential Access
IEEE Transactions on Computers
IEEE Transactions on Computers
Interconnections for Parallel Memories to Unscramble p-Ordered Vectors
IEEE Transactions on Computers
The Organization and Use of Parallel Memories
IEEE Transactions on Computers
The Organization of High-Speed Memory for Parallel Block Transfer of Data
IEEE Transactions on Computers
Dynamic Memories with Enhanced Data Access
IEEE Transactions on Computers
An analytical model for a class of processor-memory interconnection networks
IEEE Transactions on Computers
Cost-Performance Bounds for Multimicrocomputer Networks
IEEE Transactions on Computers
Binary Trees and Parallel Scheduling Algorithms
IEEE Transactions on Computers
Notes on Shuffle/Exchange-Type Switching Networks
IEEE Transactions on Computers
Communication Structures for Large Networks of Microcomputers
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
The Prime Memory System for Array Access
IEEE Transactions on Computers
The Universality of the Shuffle-Exchange Network
IEEE Transactions on Computers
A Self-Routing Benes Network and Parallel Permutation Algorithms
IEEE Transactions on Computers
Parallel Permutations of Data: A Benes Network Control Algorithm for Frequently Used Permutations
IEEE Transactions on Computers
A Uniform Representation of Single-and Multistage Interconnection Networks Used in SIMD Machines
IEEE Transactions on Computers
The Theory Underlying the Partitioning of Permutation Networks
IEEE Transactions on Computers
Fast Random and Sequential Access to Dynamic Memories of Any Size
IEEE Transactions on Computers
A Two-Level Microprogrammed Multiprocessor Computer with Nonnumeric Functions
IEEE Transactions on Computers
Routing Schemes for the Augmented Data Manipulator Network in an MIMD System
IEEE Transactions on Computers
Dynamic memories with faster random and sequential access
IBM Journal of Research and Development
Shuffling with the Illiac and PM2I SIMD Networks
IEEE Transactions on Computers
IEEE Transactions on Computers - Special issue on parallel processors and processing
Hi-index | 15.03 |
In this paper, a control mechanism for a shuffle-exchange interconnection network of N cells is proposed. With this network it is possible to realize some important permutations in log2 N shuffle-exchange steps. In the control mechanism presented, the control variables at step k are determined by a Boolean operation of the control variables at step k 驴1. The Boolean operation is very simple so that little additional hardware is required for this computation. This control scheme requires only one bit per cell instead of a destination tag of log2 N bits required by a control mechanism presented previously. The network can be used for the interconnection of memory modules and processors in an array computer, and for the accessing of blocks of consecutive data in large dynamic memories. It is also shown that the shuffle-exchange interconnection network permits the efficient partitioning of an array computer into subarrays to allow for the simultaneous computation of several identical problems.