Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
Dynamic Memories with Enhanced Data Access
IEEE Transactions on Computers
Fast Random and Sequential Access to Dynamic Memories of Any Size
IEEE Transactions on Computers
Dynamic Memory Interconnections for Rapid Access
IEEE Transactions on Computers
Traversing Binary Tree Structures with Shift-Register Memories
IEEE Transactions on Computers
Dynamic Memories with Fast Random and Sequential Access
IEEE Transactions on Computers
A Shuffle-Exchange Network with Simplified Control
IEEE Transactions on Computers
Dynamic memories with faster random and sequential access
IBM Journal of Research and Development
IEEE Transactions on Computers - Special issue on parallel processors and processing
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We propose a new architecture for dynamic memories in which the contents of any cell in memory can be accessed by applying a sequence of two primitive memory operations. The advantage of our memory over previous designs is its fast sequential access. Any word in an n cell memory can be accessed in 0(log n) steps. However, once two consecutive words have been accessed, following words can be accessed in one step per word.