A complexity theory for VLSI
Dynamic Memories with Rapid Random and Sequential Access
IEEE Transactions on Computers
Processes for Random and Sequential Accessing in Dynamic Memories
IEEE Transactions on Computers
Fast Random and Sequential Access to Dynamic Memories of Any Size
IEEE Transactions on Computers
Dynamic Memories with Fast Random and Sequential Access
IEEE Transactions on Computers
The Generation of Permutations in Magnetic Bubble Memories
IEEE Transactions on Computers
Dynamic Memories with Enhanced Data Access
IEEE Transactions on Computers
Dynamic memories with faster random and sequential access
IBM Journal of Research and Development
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In this correspondence we consider a model for dynamic memories that are characterized by small cell fan-out and a small number of I/O ports. Many schemes have been proposed in the literature to interconnect dynamic memory cells. These usually exhibit a tradeoff between random and block access times. We propose a scheme that combines the interconnection scheme of a previous work with the idea of interleaving. With this we show that both random and block access times can be optimized. We analyze access times for our scheme and compare them to those for other schemes in the literature. We define delay between two block accesses and compare the dynamic memory organization schemes on the basis of delay.