Program Suitability for Parallel Processing
IEEE Transactions on Computers
IEEE Transactions on Computers
Detection and Parallel Execution of Independent Instructions
IEEE Transactions on Computers
The Inhibition of Potential Parallelism by Conditional Jumps
IEEE Transactions on Computers
A multiprocessor system design
AFIPS '63 (Fall) Proceedings of the November 12-14, 1963, fall joint computer conference
A survey of techniques for recognizing parallel processable streams in computer programs
AFIPS '69 (Fall) Proceedings of the November 18-20, 1969, fall joint computer conference
Limits and Graph Structure of Available Instruction-Level Parallelism (Research Note)
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
Performance enhancement of SISD processors
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Trace Scheduling: A Technique for Global Microcode Compaction
IEEE Transactions on Computers
Measuring the Parallelism Available for Very Long Instruction Word Architectures
IEEE Transactions on Computers
More is less: reducing latency via redundancy
Proceedings of the 11th ACM Workshop on Hot Topics in Networks
Proceedings of the ninth ACM conference on Emerging networking experiments and technologies
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This note investigates the increase in parallel execution rate as a function of the size of an instruction dispatch stack with lookahead hardware. Under the constraint that instructions are not dispatched until all preceding conditional branches are resolved, stack sizes as small as 2 or 4 achieve most of the parallelism that a hypothetically infinite stack would.