Performance enhancement of SISD processors

  • Authors:
  • W. G. Rosocha;E. S. Lee

  • Affiliations:
  • -;-

  • Venue:
  • ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
  • Year:
  • 1979

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Abstract

The automatic coordination of instruction execution of SISD processors is examined in the context of minimizing the effects of branch execution. Three areas, instruction prefetch, branch resolution, and issuer organization are examined for possible improvement. The thrust of these techniques is to extend conditional processing and to use look-ahead to detect branches. A structured instruction buffer, the converger, is used to buffer one or more levels of conditionally prefetched instructions. Conditioning schemes that permit a large degree of branch resolution overlap with instruction execution are presented. Issuer organization extensions, that promote a high issue rate and conditional instruction execution are presented.