The effect of instruction fetch strategies upon the performance of pipelined instruction units

Authors:
Ramakrishna B. Rau;George E. Rossmann
Affiliations:
Stanford University;Palyn Associates, Inc.
Venue:
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Year:
1977

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Abstract

The interpretation of a machine instruction requires fetching the instruction, decoding the instruction, and then executing it. In addition, if the instruction requires one or more operands, their addresses must be generated and the operands fetched. A large number of processors have been designed to perform some or all of these functions simultaneously on successive instructions. These pipelined processor architectures would appear to permit the decoding of a new instruction each machine cycle.