Organization and VLSI implementation of MIPS
Advances in VLSI and Computer Systems
Reduced instruction set computer architectures for VLSI
Reduced instruction set computer architectures for VLSI
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
IBM RISC workstation features 40-bit virtual addressing
Computer Design
The case for the reduced instruction set computer
ACM SIGARCH Computer Architecture News
MICRO 15 Proceedings of the 15th annual workshop on Microprogramming
Measurement and analysis of instruction use in the VAX-11/780
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Hardware/software tradeoffs for increased performance
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
A case study of VAX-11 instruction set usage for compiler execution
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
A study of branch prediction strategies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
RISC I: A Reduced Instruction Set VLSI Computer
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
The PDP-11: A case study of how not to design condition codes
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
A Characterization of Processor Performance in the vax-11/780
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
The effect of instruction fetch strategies upon the performance of pipelined instruction units
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
An instruction timing model of CPU performance
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
MIPS: a VLSI processor architecture
MIPS: a VLSI processor architecture
Design of a high performance VLSI processor
Design of a high performance VLSI processor
Code optimization of pipeline constraints
Code optimization of pipeline constraints
Comparing software and hardware schemes for reducing the cost of branches
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Reducing the branch penalty by rearranging instructions in a double-width memory
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Performance from architecture: comparing a RISC and a CISC with similar hardware organization
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Two-level adaptive training branch prediction
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Branch Strategies: Modeling and Optimization (Pipeline Processing)
IEEE Transactions on Computers
Alternative implementations of two-level adaptive branch prediction
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
A comprehensive instruction fetch mechanism for a processor supporting speculative execution
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Branch with masked squashing in superpipelined processors
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Branch classification: a new mechanism for improving branch predictor performance
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Minimizing branch misprediction penalties for superpipelined processors
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Prophetic branches: a branch architecture for code compaction and efficient execution
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Alternative implementations of two-level adaptive branch prediction
25 years of the international symposia on Computer architecture (selected papers)
Control flow optimization for supercomputer scalar processing
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Instruction fetch unit for parallel execution of branch instructions
ICS '89 Proceedings of the 3rd international conference on Supercomputing
A Comparison of RISC Architectures
IEEE Micro
Branch Target Buffer Design and Optimization
IEEE Transactions on Computers
Instruction Scheduling for Low Power
Journal of VLSI Signal Processing Systems
Continuous signature monitoring: efficient concurrent-detection of processor control errors
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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Branch instructions form a significant fraction of executed instructions, and their design is thus a crucial component of any architecture. This paper examines three alternatives in the design of branch instructions: delayed vs. non-delayed branches, one- vs. two-instruction branches, and the use or non-use of condition codes. Simulation and analytical techniques are used to provide quantitative comparisons between these choices.