Empirical evaluation of some features of instruction set processor architectures
Communications of the ACM
Computer structures: What have we learned from the PDP-11?
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Experience in the design, implementation and use of PL-11, a programming language for the PDP-11
SIGMINI '76 Proceedings of the ACM SIGMINI/SIGPLAN interface meeting on Programming systems in the small processor environment
Ambiguous machine architecture and program efficiency
ACM SIGARCH Computer Architecture News
Arithmetic shifting considered harmful
ACM SIGPLAN Notices
Branch folding in the CRISP microprocessor: reducing branch delay to zero
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
An evaluation of branch architectures
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Should SCC set condition codes?
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
A systematic approach to the design and implementation of a computer instruction set
ACM SIGARCH Computer Architecture News
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This paper investigates a design weakness in the PDP-11 architecture, namely the condition code bits. Experience with the machine has demonstrated a number of “traps” for the unwary programmer stemming directly from an inconsistent and sometimes confusing scheme of condition code settings. This is particularly annoying in view of the otherwise clean architectural characteristics of the machine. A number of “principles” are proposed that would correct the deficiencies and could therefore be used as a guide for designing future machines. The paper also presents some measurements based on actual programmatic usage of the PDP-11 that question the validity of a condition code scheme as an efficient architectural technique.