BLISS: a language for systems programming
Communications of the ACM
A method for comparing the internal operating speeds of computers
Communications of the ACM
More data on the O/W ratios: a note on a paper by Flynn
ACM SIGARCH Computer Architecture News
Evaluation of instruction set processor architecture by program tracing.
Evaluation of instruction set processor architecture by program tracing.
Computer structures: Readings and examples (McGraw-Hill computer science series)
Computer structures: Readings and examples (McGraw-Hill computer science series)
A microcode-based environment for noninvasive performance analysis
MICRO 19 Proceedings of the 19th annual workshop on Microprogramming
An analysis of MIPS and SPARC instruction set utilization on the SPEC benchmarks
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Viewing instruction set design as an optimization problem
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
DISC: dynamic instruction stream computer
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Solutions Relating Static and Dynamic Machine Code Measurements
IEEE Transactions on Computers
Linear logic and permutation stacks—the Forth shall be first
ACM SIGARCH Computer Architecture News - Special issue: panel sessions of the 1991 workshop on multithreaded computers
A Parallel Virtual Machine for Programs Composed of Abstract Data Types
IEEE Transactions on Computers
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
A characterization of processor performance in the VAX-11/780
25 years of the international symposia on Computer architecture (selected papers)
Design of a Machine-Independent Optimizing System for Emulator Development
ACM Transactions on Programming Languages and Systems (TOPLAS)
The evolution of the DECsystem 10
Communications of the ACM - Special issue on computer architecture
The AT&T WE32200 Design Challenge
IEEE Micro
Micronets: a model for decentralising control in asynchronous processor architectures
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
RISC assessment: A high-level language experiment
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Hardware/software tradeoffs for increased performance
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
A case study of VAX-11 instruction set usage for compiler execution
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
An architecture with many operand registers to efficiently execute block-structured languages
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Direct execution of C-string compiler texts
MICRO 12 Proceedings of the 12th annual workshop on Microprogramming
Data structure architectures - a major operational principle
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
The PDP-11: A case study of how not to design condition codes
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
MBALM/1700: A microprogrammed LISP machine for the Burroughs B1726
MICRO 10 Proceedings of the 10th annual workshop on Microprogramming
A Characterization of Processor Performance in the vax-11/780
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Mapping HLL constructs into microcode for improved execution speed
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
Metrics for Microprogrammed Instruction Sets
ACM SIGMICRO Newsletter
ACM SIGARCH Computer Architecture News
Dynamic Profile of Instruction Sequences for the IBM System/370
IEEE Transactions on Computers
On the Behaviours Produced by Instruction Sequences under Execution
Fundamenta Informaticae
| Hi-index | 48.23 |
This paper presents methods for empirical evaluation of features of Instruction Set Processors (ISPs). ISP features are evaluated in terms of the time used or saved by having or not having the feature. The methods are based on analysis of traces of program executions. The concept of a register life is introduced, and used to answer questions like: How many registers are used simultaneously? How many would be sufficient all of the time? Most of the time? What would the overhead be if the number of registers were reduced? What are registers used for during their lives? The paper also discusses the problem of detecting desirable but non-existing instructions. Other problems are briefly discussed. Experimental results are presented, obtained by analyzing 41 programs running on the DECsystem10 ISP.