Organization and VLSI implementation of MIPS
Advances in VLSI and Computer Systems
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
Empirical evaluation of some features of instruction set processor architectures
Communications of the ACM
Implications of structured programming for machine architecture
Communications of the ACM
A reduced register file for RISC architectures
ACM SIGARCH Computer Architecture News
Advances in Computer Architecture
Advances in Computer Architecture
Computer Programming and Architecture: The VAX-11
Computer Programming and Architecture: The VAX-11
The case for the reduced instruction set computer
ACM SIGARCH Computer Architecture News
Comments on "the case for the reduced instruction set computer," by Patterson and Ditzel
ACM SIGARCH Computer Architecture News
Architecture of a VLSI instruction cache for a RISC
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
RISC assessment: A high-level language experiment
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Measurement and analysis of instruction use in the VAX-11/780
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
An analysis of a mesa instruction set using dynamic instruction frequencies
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
RISC I: A Reduced Instruction Set VLSI Computer
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Retrospective on high-level language computer architecture
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
An instruction timing model of CPU performance
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Analysis and performance of computer instruction sets.
Analysis and performance of computer instruction sets.
Reduced instruction set computer architectures for vlsi (microprocessor, risc, multiple-windows - of - registers)
An overview of RISC architecture
SAC '92 Proceedings of the 1992 ACM/SIGAPP Symposium on Applied computing: technological challenges of the 1990's
Microprogramming heritage of RISC design
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
| Hi-index | 0.00 |
The design principles of reduced-instruction-set computer (RISC) architectures as they apply to VLSI implementation for high-level languages (HLLs) are presented. The nature of general-purpose HLL computations is discussed in terms of static and dynamic program measurements, and the HLL features that need efficient support are identified. CISC (complex-instruction-set computer) and RISC approaches to general-purpose HLL computers are outlined, the effects of instruction-set reduction on both code size and execution time are evaluated, and the delayed-jump concept is introduced. The Berkeley RISC architecture is presented as an example.