A functional instruction mix and some related topics
SIGMETRICS '76 Proceedings of the 1976 ACM SIGMETRICS conference on Computer performance modeling measurement and evaluation
Using a computer to design computer instruction sets
Using a computer to design computer instruction sets
Line (block) size choice for CPU cache memories
IEEE Transactions on Computers
An evaluation of branch architectures
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Characterization of branch and data dependencies on programs for evaluating pipeline performance
IEEE Transactions on Computers
Cache performance of operating system and multiprogramming workloads
ACM Transactions on Computer Systems (TOCS)
The Clipper processor: instruction set architecture and implementation
Communications of the ACM
Machine Characterization Based on an Abstract High-Level Language Machine
IEEE Transactions on Computers
Fast instruction cache performance evaluation using compile-time analysis
SIGMETRICS '92/PERFORMANCE '92 Proceedings of the 1992 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Solutions Relating Static and Dynamic Machine Code Measurements
IEEE Transactions on Computers
Avoiding unconditional jumps by code replication
PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation
History cache: hardware support for reverse execution
ACM SIGARCH Computer Architecture News
Performance of the VAX-11/780 translation buffer: simulation and measurement
ACM Transactions on Computer Systems (TOCS)
Analysis of benchmark characteristics and benchmark performance prediction
ACM Transactions on Computer Systems (TOCS)
A characterization of processor performance in the VAX-11/780
25 years of the international symposia on Computer architecture (selected papers)
Direct execution models of processor behavior and performance
WSC '87 Proceedings of the 19th conference on Winter simulation
Characterizing the Storage Process and Its Effect on the Update of Main Memory by Write Through
Journal of the ACM (JACM)
The contribution to performance of instruction set usage in System/370
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
ACM Computing Surveys (CSUR)
Cache Performance in the VAX-11/780
ACM Transactions on Computer Systems (TOCS)
A Comparison of RISC Architectures
IEEE Micro
Branch Target Buffer Design and Optimization
IEEE Transactions on Computers
Measuring Cache and TLB Performance and Their Effect on Benchmark Runtimes
IEEE Transactions on Computers
Performance Characterization of Optimizing Compilers
IEEE Transactions on Software Engineering
The case for the reduced instruction set computer
ACM SIGARCH Computer Architecture News
Software Counting rules: Will history repeat itself?
SCORE '82 Selected papers of the 1982 ACM SIGMETRICS workshop on Software Metrics: part 1
Measurement and analysis of instruction use in the VAX-11/780
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
A case study of VAX-11 instruction set usage for compiler execution
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
A Characterization of Processor Performance in the vax-11/780
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Analysis of Multiprocessors with Private Cache Memories
IEEE Transactions on Computers
Dynamic Profile of Instruction Sequences for the IBM System/370
IEEE Transactions on Computers
Platform Independent Timing of Java Virtual Machine Bytecode Instructions
Electronic Notes in Theoretical Computer Science (ENTCS)
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A model of high-performance computers is derived from instruction timing formulas, with compensation for pipeline and cache memory effects. The model is used to predict the performance of the IBM 370/168 and the Amdahl 470 V/6 on specific programs,/and the results are verified by comparison with actual performance. Data collected about program behavior is combined with the performance analysis to highlight some of the problems with high-performance implementations of such architectures.