Computer programming and architecture: The VAX
Computer programming and architecture: The VAX
ACM Computing Surveys (CSUR)
A case study of VAX-11 instruction set usage for compiler execution
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
An instruction timing model of CPU performance
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
A SIMULATOR OF MULTIPLE INTERACTIVE USERS TO DRIVE A TIME-SHARED COMPUTER SYSTEM
A SIMULATOR OF MULTIPLE INTERACTIVE USERS TO DRIVE A TIME-SHARED COMPUTER SYSTEM
ATUM: a new technique for capturing address traces using microcode
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Software-controlled caches in the VMP multiprocessor
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Line (block) size choice for CPU cache memories
IEEE Transactions on Computers
Multiprocessor cache design considerations
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
ACM Transactions on Computer Systems (TOCS)
Cache performance of operating system and multiprogramming workloads
ACM Transactions on Computer Systems (TOCS)
Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems
IEEE Transactions on Computers
A simulation study of two-level caches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Measuring VAX 8800 performance with a histogram hardware monitor
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Characterizing the synchronization behavior of parallel programs
PPEALS '88 Proceedings of the ACM/SIGPLAN conference on Parallel programming: experience with applications, languages and systems
ACM Transactions on Computer Systems (TOCS)
Inexpensive implementations of set-associativity
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
TRAPEDS: producing traces for multicomputers via execution driven simulation
SIGMETRICS '89 Proceedings of the 1989 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Evaluating Associativity in CPU Caches
IEEE Transactions on Computers
Quick and easy cache performance analysis
ACM SIGARCH Computer Architecture News
Analysis of multithreaded architectures for parallel computing
SPAA '90 Proceedings of the second annual ACM symposium on Parallel algorithms and architectures
Address Tracing for Parallel Machines
Computer - Special issue on experimental research in computer architecture
Modeling and measurement of the impact of Input/Output on system performance
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Experience with a software-defined machine architecture
ACM Transactions on Programming Languages and Systems (TOPLAS)
Characterizing the caching and synchronization performance of a multiprocessor operating system
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Cache write policies and performance
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
The impact of operating system structure on memory system performance
SOSP '93 Proceedings of the fourteenth ACM symposium on Operating systems principles
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Trap-driven simulation with Tapeworm II
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Contrasting characteristics and cache performance of technical and multi-user commercial workloads
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Execution-driven simulation of multiprocessors: address and timing analysis
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Performance effects of architectural complexity in the Intel 432
ACM Transactions on Computer Systems (TOCS)
Performance of the VAX-11/780 translation buffer: simulation and measurement
ACM Transactions on Computer Systems (TOCS)
Instruction fetching: coping with code bloat
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The influence of caches on the performance of heaps
Journal of Experimental Algorithmics (JEA)
Trap-driven memory simulation with Tapeworm II
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Constructing instruction traces from cache-filtered address traces (CITCAT)
ACM SIGARCH Computer Architecture News
A characterization of processor performance in the VAX-11/780
25 years of the international symposia on Computer architecture (selected papers)
Optimizing the Instruction Cache Performance of the Operating System
IEEE Transactions on Computers
The influence of caches on the performance of sorting
SODA '97 Proceedings of the eighth annual ACM-SIAM symposium on Discrete algorithms
Cache evaluation and the impact of workload choice
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
Cache performance for multimedia applications
ICS '01 Proceedings of the 15th international conference on Supercomputing
A national trace collection and distribution resource
ACM SIGARCH Computer Architecture News
Facilitating level three cache studies using set sampling
Proceedings of the 32nd conference on Winter simulation
Using the BACH trace collection mechanism to characterize the SPEC 2000 integer benchmarks
Workload characterization of emerging computer applications
A Quantitative Evaluation of Cache Types for High-Performance Computer Systems
IEEE Transactions on Computers
IEEE Transactions on Computers
Efficient Stack Simulation for Set-Associative Virtual Address Caches With Real Tags
IEEE Transactions on Computers
RECET - A Real-Time Cache Evaluation Tool
MASCOTS '95 Proceedings of the 3rd International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
A Characterization of Processor Performance in the vax-11/780
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Cache hit ratios with geometric task switch intervals
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Optimizing instruction cache performance for operating system intensive workloads
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
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