ATUM: a new technique for capturing address traces using microcode
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
ACM Transactions on Computer Systems (TOCS)
Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems
IEEE Transactions on Computers
Measuring VAX 8800 performance with a histogram hardware monitor
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Efficient (stack) algorithms for analysis of write-back and sector memories
ACM Transactions on Computer Systems (TOCS)
Mache: no-loss trace compaction
SIGMETRICS '89 Proceedings of the 1989 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Evaluating Associativity in CPU Caches
IEEE Transactions on Computers
Quick and easy cache performance analysis
ACM SIGARCH Computer Architecture News
Efficient trace-driven simulation methods for cache performance analysis
ACM Transactions on Computer Systems (TOCS)
Analysis of multi-megabyte secondary CPU cache memories
Analysis of multi-megabyte secondary CPU cache memories
Address tracing of parallel systems via TRAPEDS
Microprocessors & Microsystems
Generation and analysis of very long address traces
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Cache Performance in the VAX-11/780
ACM Transactions on Computer Systems (TOCS)
Transient behavior of cache memories
ACM Transactions on Computer Systems (TOCS)
Incomplete Trace Data and Trace Driven Simulation
MASCOTS '93 Proceedings of the International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems
Methodology and empirical results of program behaviour measurements
PERFORMANCE '80 Proceedings of the 1980 international symposium on Computer performance modelling, measurement and evaluation
Cache hit ratios with geometric task switch intervals
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Trace compaction using cache filtering with blocking
Trace compaction using cache filtering with blocking
Analysis of cache replacement-algorithms
Analysis of cache replacement-algorithms
Instruction Cache Replacement Policies and Organizations
IEEE Transactions on Computers
Two Methods for the Efficient Analysis of Memory Address Trace Data
IEEE Transactions on Software Engineering
Evaluation techniques for storage hierarchies
IBM Systems Journal
Real time aspects of cluster based caches
RTCSA '95 Proceedings of the 2nd International Workshop on Real-Time Computing Systems and Applications
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Previously used methods to analyse and model the behaviour and performance of various cache configurations have been limited in many ways. Either the method itself produces inaccurate results, or assumptions regarding the memory referencing behaviour of the workload has been made. Many trace-driven simulations have used incomplete traces and have resulted in overoptimistic results. These results have in many cases been obtained using rather crude assumptions about the behaviour of workloads in real computing environments. A new approach is presented in this paper that not only captures complete and accurate address traces but also preprocesses and simulates various cache parameters in real time. The RECET (Real-time Cache Evaluation Tool) project is realized as a flexible, modular and configurable tool which can be used to capture and preprocess address traces, and simulate multiple cache configurations in real time from any source without disturbing the operation of the target computer.