Performance effects of architectural complexity in the Intel 432

  • Authors:

  • Robert P. Colwell;Edward F. Gehringer;E. Douglas Jensen

  • Affiliations:

  • Multiflow Computer, Inc., 175 N. Main St., Branford, CT;Department of Electrical & Computer Engineering, Department of Computer Science, North Carolina State University, Raleigh, NC;Kendall Square Research Corp., 1 Kendall Square, Cambridge, MA

  • Venue:
  • ACM Transactions on Computer Systems (TOCS)
  • Year:
  • 1988

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Abstract

The Intel 432 is noteworthy as an architecture incorporating a large amount of functionality that most other systems perform by software. It has, in effect, “migrated” this functionality from the software into the microcode and hardware. The benefits of functional migration have recently been a subject of intense controversy, with critics claiming that a complex architecture is inherently less efficient than a simple architecture with good software support. This paper examines the performance impact of the incorporation of several kinds of functionality into the Intel 432. Among these are the addressing structure, the caches, instruction alignment, the buses, and the way that garbage collection is handled. A set of several benchmarks is used to quantify the performance effect of each of these decisions. The results indicate that the 432 could have been speeded up very significantly if a small number of implementation decisions had been made differently, and if incrementally better technology had been used in its construction. Even with these modifications, however, the 432 would still have only one-fourth to one times the speed of its contemporaries. These figures may represent the real cost of the 432's style of object-based programming environment.