Measurement and analysis of instruction use in the VAX-11/780
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Register allocation for free: The C machine stack cache
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
An analysis of a mesa instruction set using dynamic instruction frequencies
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Fast object-oriented procedure calls: lessons from the Intel 432
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Distributed shared memory in a loosely coupled distributed system
SIGCOMM '87 Proceedings of the ACM workshop on Frontiers in computer communications technology
The Clipper processor: instruction set architecture and implementation
Communications of the ACM
Performance effects of architectural complexity in the Intel 432
ACM Transactions on Computer Systems (TOCS)
PIPE: a VLSI decoupled architecture
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Dhrystone: a synthetic systems programming benchmark
Communications of the ACM
On the use of benchmarks for measuring system performance
ACM SIGARCH Computer Architecture News
An analysis of C machine support for other block-structured languages
ACM SIGARCH Computer Architecture News
ACM SIGARCH Computer Architecture News
An Analysis of Access Control Models
ACISP '99 Proceedings of the 4th Australasian Conference on Information Security and Privacy
Hierarchical function distribution - a design principle for advanced multicomputer architectures
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Hints for computer system design
SOSP '83 Proceedings of the ninth ACM symposium on Operating systems principles
Peering through the RISC/CISC fog: an outline of research
ACM SIGARCH Computer Architecture News
ACM SIGARCH Computer Architecture News
Gate-level redundancy: a new design-for reliability paradigm for nanotechnologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fault-tolerant interconnect mechanism for NMR nanoarchitectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HISC: A computer architecture using operand descriptor
Computers and Electrical Engineering
Architectural solution to object-oriented programming
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
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We describe art experiment to test the 432 as a high-level language uniprocessor by comparing it with the 8086, 68000, and VAX-11/780 for four integer and character programs written in Ada, C, and Pascal.