The C programming language
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
RISC I: A Reduced Instruction Set VLSI Computer
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Design of a user-microprogrammable building block
MICRO 13 Proceedings of the 13th annual workshop on Microprogramming
An architecture with many operand registers to efficiently execute block-structured languages
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
On the use of registers vs. cache to minimize memory traffic
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
An architectural perspective on a memory access controller
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
A performance analysis of automatically managed top of stack buffers
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
WISQ: a restartable architecture using queues
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
The hardware architecture of the CRISP microprocessor
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Reducing execution parameter through correspondence in computer architecture
IBM Journal of Research and Development
Design tradeoffs to support the C programming language in the CRISP microprocessor
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Performance evaluation of on-chip register and cache organizations
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Data buffer performance for sequential Prolog architectures
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
A novel effective address calculation mechanism for RISC microprocessors
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
A simple interprocedural register allocation algorithm and its effectiveness for LISP
ACM Transactions on Programming Languages and Systems (TOPLAS)
Data buffering: run-time versus compile-time support
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Evaluation of memory system for integrated Prolog processor IPP
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Architectural support for reduced register saving/restoring in single-window register files
ACM Transactions on Computer Systems (TOCS)
Flexible register management for sequential programs
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
DISC: dynamic instruction stream computer
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Processor Architecture and Data Buffering
IEEE Transactions on Computers
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Stack caching for interpreters
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Zero-cycle loads: microarchitecture support for reducing load latency
Proceedings of the 28th annual international symposium on Microarchitecture
Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences
Proceedings of the 24th annual international symposium on Computer architecture
Decoupling local variable accesses in a wide-issue superscalar processor
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Access region locality for high-bandwidth processor memory system design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
An object oriented architecture
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Early load address resolution via register tracking
Proceedings of the 27th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
Dhrystone: a synthetic systems programming benchmark
Communications of the ACM
The store-load address table and speculative register promotion
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
L1 data cache decomposition for energy efficiency
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
A High-Bandwidth Memory Pipeline for Wide Issue Processors
IEEE Transactions on Computers
Optimization strategies of stack control
PPPJ '02/IRE '02 Proceedings of the inaugural conference on the Principles and Practice of programming, 2002 and Proceedings of the second workshop on Intermediate representation engineering for virtual machines, 2002
A performance evaluation of the Intel iAPX 432
ACM SIGARCH Computer Architecture News
An analysis of C machine support for other block-structured languages
ACM SIGARCH Computer Architecture News
Hints for computer system design
SOSP '83 Proceedings of the ninth ACM symposium on Operating systems principles
Cache memories: A tutorial and survey of current research directions
ACM '82 Proceedings of the ACM '82 conference
Peering through the RISC/CISC fog: an outline of research
ACM SIGARCH Computer Architecture News
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Scalable network-based buffer overflow attack detection
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems
Transactions on High-Performance Embedded Architectures and Compilers I
Impact of memory systems on computer architecture and system organization
IBM Systems Journal
Leveraging high performance data cache techniques to save power in embedded systems
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Stack filter: Reducing L1 data cache power consumption
Journal of Systems Architecture: the EUROMICRO Journal
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The Bell Labs C Machine project is investigating computer architectures to support the C programming language.1 One of the goals is to match an efficient architecture to the language and the compiler technology available. Measurements of different C programs show that roughly one out of every twenty instructions executed is either a procedure call or return.2 Procedure call overhead is therefore a very important consideration in the overall machine design. A second and related area of primary concern in overall machine efficiency is the register allocation strategy. While use of additional registers can offer considerable improvement in execution times, adding registers usually has the adverse effects of increasing the procedure call overhead due to register saving and creating an undue burden on the compiler. In this paper we describe a piece of the C Machine architecture which effectively eliminates the register allocation problem, and improves procedure calling by drastically reducing storage references required by traditional register saving. The technique can be generalized for other languages and architectures, though we will only directly address those issues involving the C language.