On the use of registers vs. cache to minimize memory traffic

  • Authors:

  • J. R. Goodman;W. C. Hsu

  • Affiliations:

  • Computer Sciences Department, The University of Wisconsin-Madison, Madison, WI;Computer Sciences Department, The University of Wisconsin-Madison, Madison, WI

  • Venue:
  • ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
  • Year:
  • 1986

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Abstract

Single-chip computers are becoming increasingly limited by the access constraints to off-chip memory. To achieve high performance, the structure of on-chip memory must be appropriate, and it must be allocated effectively to minimize off-chip communication. We report experiments that demonstrate that on-chip memory can be effective for local variable accesses. For best use of the limited on-chip area, we suggest organizing memory as registers and argue that an effective register spilling scheme is required. We introduce a heuristic algorithm for register spilling within basic blocks and demonstrate that trace optimization techniques can extend the use of the algorithm to global allocation. Through trace simulation, we show that the use of registers can be more effective in reducing the bus traffic than cache memory of the same size.