On the use of registers vs. cache to minimize memory traffic
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
An architectural perspective on a memory access controller
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Bit-Slice Microprocessor Design
Bit-Slice Microprocessor Design
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This paper describes architectures based on a new memory structure. Memory systems which can perform multiple transfers are described and issues in processor architecture are considered. A general model for memory operations is given, and the classical single transfer memory structures are described. Based on the generalized model, new structures which allow multiple transfers to be performed as a single processor operation are developed. Some architectural considerations at the processor level to support these kinds of memory systems are then discussed. The advantages and disadvantages of these new structures as compared to conventional memories are also discussed and a preliminary performance evaluation is done. This discussion generally refers to the random access, physical, main memory in the system, although many of the results are applicable to other storage devices.