Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
Software-controlled caches in the VMP multiprocessor
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
A class of compatible cache consistency protocols and their support by the IEEE futurebus
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Line (block) size choice for CPU cache memories
IEEE Transactions on Computers
ACM Computing Surveys (CSUR)
Cache memory performance in a unix enviroment
ACM SIGARCH Computer Architecture News
Translation buffer performance in a UNIX enviroment
ACM SIGARCH Computer Architecture News
Computer Storage Systems and Technology
Computer Storage Systems and Technology
Register allocation for free: The C machine stack cache
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Experimental evaluation of on-chip microprocessor cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
An overview of the MIPS-X-MP project
An overview of the MIPS-X-MP project
Multiple operation memory structures
MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
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In this paper a CMOS memory access controller chip is described that provides the basis for achieving high-performance 68020-based (68030-based) systems. This controller matches the speed of the memory system to that of the microprocessor by providing a virtual cache mechanism where address translations are only required when there is a cache miss.This mechanism also facilitates the construction of shared-memory multiprocessor system where the controller manages a memory hierarchy consisting of cache memory, local memory, and shared global memory.