Stack filter: Reducing L1 data cache power consumption

Authors:
R. Gonzalez-Alberquilla;F. Castro;L. Pinuel;F. Tirado
Affiliations:
ArTeCS Group, University Complutense of Madrid, Spain;ArTeCS Group, University Complutense of Madrid, Spain;ArTeCS Group, University Complutense of Madrid, Spain;ArTeCS Group, University Complutense of Madrid, Spain
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2010

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Abstract

The L1 data cache is one of the most frequently accessed structures in the processor. Because of this and its moderate size it is a major consumer of power. In order to reduce its power consumption, in this paper a small filter structure that exploits the special features of the references to the stack region is proposed. This filter, which acts as a top - non-inclusive - level of the data memory hierarchy, consists of a register set that keeps the data stored in the neighborhood of the top of the stack. Our simulation results show that using a small Stack Filter (SF) of just a few registers, 10-25% data cache power savings can be achieved on average, with a negligible performance penalty.