IMPACT: an architectural framework for multiple-instruction-issue processors
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
The superblock: an effective technique for VLIW and superscalar compilation
The Journal of Supercomputing - Special issue on instruction-level parallelism
Guarded execution and branch prediction in dynamic ILP processors
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Available paralellism in video applications
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Architecture and compiler design issues in programmable media processors
Architecture and compiler design issues in programmable media processors
Runtime predictability of loops
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
Dynamic Characteristics of Loops
IEEE Transactions on Computers
Hardware and software cache prefetching techniques for MPEG benchmarks
IEEE Transactions on Circuits and Systems for Video Technology
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Stack filter: Reducing L1 data cache power consumption
Journal of Systems Architecture: the EUROMICRO Journal
Selectively fortifying reconfigurable computing device to achieve higher error resilience
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
General data structure expansion for multi-threading
Proceedings of the 34th ACM SIGPLAN conference on Programming language design and implementation
Accelerating an application domain with specialized functional units
ACM Transactions on Architecture and Code Optimization (TACO)
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The first step towards the design of video processors and systems is to achieve an understanding of the major applications, including not only the theory, but also the workload characteristics of the many image and video compression standards. Introduced in 1997, the MediaBench benchmark suite provided the first set of full application-level benchmarks for multimedia, and has consequently enabled significant research in computer architecture and compiler research for media systems. To expedite the next generation of multimedia systems research, we are developing the MediaBench II benchmark suite, incorporating benchmarks from the latest multimedia technologies, and providing both a single composite benchmark suite (MB2"c"o"m"p) as well as separate sub-suites for each area of multimedia. For video, MediaBench II Video (MB2"v"i"d"e"o) includes both the popular mainstream video compression standards, such as JPEG, H.263, and MPEG-2, and the more recent and emerging standards, including MPEG-4, JPEG-2000, and H.264. This paper first discusses the goals for MediaBench II and the design of the MB2"v"i"d"e"o sub-suite. The paper then presents the results of a comprehensive workload evaluation of MB2"v"i"d"e"o. In particular, while the workload evaluation demonstrates the high processing regularity of video workloads, as compared with general-purpose workloads, it also illustrates how the growing complexity of the emerging video standards is beginning to negatively impact video workload characteristics.