Fault Injection for Dependability Validation: A Methodology and Some Applications
IEEE Transactions on Software Engineering
Linear programming 1: introduction
Linear programming 1: introduction
Energy-efficient signal processing via algorithmic noise-tolerance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Software Criticality Analysis of COTS/SOUP
SAFECOMP '02 Proceedings of the 21st International Conference on Computer Safety, Reliability and Security
A Portable and Fault-Tolerant Microprocessor Based on the SPARC V8 Architecture
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Design and Implementation of a Fine-Grained Software Inspection Tool
IEEE Transactions on Software Engineering
System-Level Dependability Analysis with RT-Level Fault Injection Accuracy
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
SEU tolerant device, circuit and processor design
Proceedings of the 42nd annual Design Automation Conference
Multi-media Applications and Imprecise Computation
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
Computing with a trillion crummy components
Communications of the ACM - ACM's plan to go online first
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
MediaBench II video: Expediting the next generation of video systems research
Microprocessors & Microsystems
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations
SSIRI '09 Proceedings of the 2009 Third IEEE International Conference on Secure Software Integration and Reliability Improvement
Models for energy-efficient approximate computing
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
VLSI Design for Video Coding: H.264/AVC Encoding from Standard Specification to Chip
VLSI Design for Video Coding: H.264/AVC Encoding from Standard Specification to Chip
A resilience roadmap: (invited paper)
Proceedings of the Conference on Design, Automation and Test in Europe
ERSA: error resilient system architecture for probabilistic applications
Proceedings of the Conference on Design, Automation and Test in Europe
Emulating human visual perception for measuring difference inimages using an SPN graph approach
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
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With the advent of 10 nm CMOS devices and "exotic" nanodevices, the location and occurrence time of hardware defects and design faults become increasingly unpredictable, therefore posing severe challenges to existing techniques for error-resilient computing because most of them statically assign hardware redundancy and do not account for the error tolerance inherently existing in many mission-critical applications. This work proposes a novel approach to selectively fortifying a target reconfigurable computing device in order to achieve hardware-efficient error resilience for a specific target application. We intend to demonstrate that such error resilience can be significantly improved with effective hardware support. The major contributions of this work include (1) the development of a complete methodology to performsensitivity and criticality analysis of hardware redundancy, (2) a novel problem formulation and an efficient heuristic methodology to selectively allocate hardware redundancy among a target design's key components in order to maximize its overall error resilience, and (3) an academic prototype of SFC computing device that illustrates a 4 times improvement of error resilience for a H.264 encoder implemented with an FPGA device.