SEU tolerant device, circuit and processor design

Authors:
William Heidergott
Affiliations:
General Dynamics, Scottsdale, Arizona
Venue:
Proceedings of the 42nd annual Design Automation Conference
Year:
2005

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Abstract

Development of highly reliable and available systems requires consideration of the occurrence of single event upsets, the effects they have on system performance, and strategies for their prevention and mitigation. Methods of systems engineering process and the application and validation of techniques for fault tolerance are discussed as elements in the elimination and mitigation of single event upsets.