Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
A soft error rate analysis (SERA) methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Circuit design and modeling for soft errors
IBM Journal of Research and Development
Analog Design Centering and Sizing
Analog Design Centering and Sizing
Efficient design-specific worst-case corner extraction for integrated circuits
Proceedings of the 46th Annual Design Automation Conference
Vision for cross-layer optimization to address the dual challenges of energy and reliability
Proceedings of the Conference on Design, Automation and Test in Europe
Cross-layer resilience challenges: metrics and optimization
Proceedings of the Conference on Design, Automation and Test in Europe
Cross-layer error resilience for robust systems
Proceedings of the International Conference on Computer-Aided Design
Limit study of energy & delay benefits of component-specific routing
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Selectively fortifying reconfigurable computing device to achieve higher error resilience
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Reliability challenges of real-time systems in forthcoming technology nodes
Proceedings of the Conference on Design, Automation and Test in Europe
Modeling and analysis of fault-tolerant distributed memories for networks-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Reliability challenges for electric vehicles: from devices to architecture and systems software
Proceedings of the 50th Annual Design Automation Conference
Proceedings of the 21st International conference on Real-Time Networks and Systems
Modeling the impact of permanent faults in caches
ACM Transactions on Architecture and Code Optimization (TACO)
A column parity based fault detection mechanism for FIFO buffers
Integration, the VLSI Journal
NoC-based fault-tolerant cache design in chip multiprocessors
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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Technology scaling has an increasing impact on the resilience of CMOS circuits. This outcome is the result of (a) increasing sensitivity to various intrinsic and extrinsic noise sources as circuits shrink, and (b) a corresponding increase in parametric variability causing behavior similar to what would be expected with hard (topological) faults. This paper examines the issue of circuit resilience, then proposes and demonstrates a roadmap for evaluating fault rates starting at the 45nm and going down to the 12nm nodes. The complete infrastructure necessary to make these predictions is placed in the open source domain, with the hope that it will invigorate research in this area.