Review and future prospects of low-voltage RAM circuits
IBM Journal of Research and Development
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Modeling and analysis of non-rectangular gate for post-lithography circuit simulation
Proceedings of the 44th annual Design Automation Conference
Design rule optimization of regular layout for leakage reduction in nanoscale design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Joint design-time and post-silicon optimization for digitally tuned analog circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
Reliability of NAND-2 CMOS gates from threshold voltage variations
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
A resilience roadmap: (invited paper)
Proceedings of the Conference on Design, Automation and Test in Europe
Statistical analysis of hold time violations
Journal of Computational Electronics
Impact of RDF and RTS on the performance of SRAM cells
Journal of Computational Electronics
Layout aware line-edge roughness modeling and poly optimization for leakage minimization
Proceedings of the 48th Design Automation Conference
Design sensitivity of single event transients in scaled logic circuits
Proceedings of the 48th Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method
Proceedings of the 49th Annual Design Automation Conference
Efficient memory repair using cache-based redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations that are too expensive computationally for statistical circuit design. In this work, we develop an efficient SPICE simulation method and statistical transistor model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by sub-wavelength lithography and gate etching process. By understanding the physical principles of atomistic simulations, we (a) identify the appropriate method to divide a non-uniform gate into slices in order to map those fluctuations into the device model; (b) extract the variation of Vth from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to Vth and (c) propose a compact model of Vth variation that is scalable with gate size and the amount of dopant and gate length fluctuations. The proposed SPICE simulation method is fully validated against atomistic simulation results. Given the post-lithography gate geometry, this approach correctly models the variation of device output current in all operating regions. Based on the new results, we further project the amount of Vth variation at advanced technology nodes, to help shed light on the challenges of future robust circuit design.