Modeling and analysis of non-rectangular gate for post-lithography circuit simulation
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
Proceedings of the 46th Annual Design Automation Conference
Energy reduction for STT-RAM using early write termination
Proceedings of the 2009 International Conference on Computer-Aided Design
Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The STeTSiMS STT-RAM simulation and modeling system
Proceedings of the International Conference on Computer-Aided Design
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Asymmetric-access aware optimization for STT-RAM caches with process variations
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
C1C: A configurable, compiler-guided STT-RAM L1 cache
ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the International Conference on Computer-Aided Design
ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications
Proceedings of the International Conference on Computer-Aided Design
Unleashing the potential of MLC STT-RAM caches
Proceedings of the International Conference on Computer-Aided Design
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Process variations and thermal fluctuations significantly affect the write reliability of spin-transfer torque random access memory (STT-RAM). Traditionally, modeling the impacts of these variations on STT-RAM designs requires expensive Monte-Carlo runs with hybrid magnetic-CMOS simulation steps. In this paper, we propose a fast and scalable semi-analytical simulation method--PS3-RAM, for STT-RAM write reliability analysis. Simulation results show that PS3-RAM offers excellent agreement with the conventional simulation method without running the costly macro-magnetic and SPICE simulations. Our method can accurately estimate the STT-RAM write error rate at both MTJ switching directions under different temperatures while receiving a speedup of multiple orders of magnitude (five order or more). PS3-RAM shows great potentials in the STT-RAM reliability analysis at the early design stage of memory or micro-architecture.