Logic-based eDRAM: origins and rationale for use
IBM Journal of Research and Development - Electrochemical technology in microelectronics
Scalable high performance main memory system using phase-change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Energy reduction for STT-RAM using early write termination
Proceedings of the 2009 International Conference on Computer-Aided Design
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
Proceedings of the 37th annual international symposium on Computer architecture
An energy efficient cache design using spin torque transfer (STT) RAM
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Accelerating enterprise solid-state disks with non-volatile merge caching
GREENCOMP '10 Proceedings of the International Conference on Green Computing
Relaxing non-volatility for fast and energy-efficient STT-RAM caches
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method
Proceedings of the 49th Annual Design Automation Conference
MetaData persistence using storage class memory: experiences with flash-backed DRAM
Proceedings of the 1st Workshop on Interactions of NVM/FLASH with Operating Systems and Workloads
Proceedings of the International Conference on Computer-Aided Design
2T-1R STT-MRAM memory cells for enhanced on/off current ratio
Microelectronics Journal
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There is growing interest in emerging non-volatile memory technologies such as Phase-Change Memory, Memristors, and Spin-Transfer Torque RAM (STT-RAM). STT-RAM, in particular, is experiencing rapid development that can be difficult for memory systems researchers to take advantage of. What is needed are techniques that enable designers to explore the potential of recent STT-RAM designs and adjust the performance without needing a detailed understanding of the physics. In this paper, we present the STeTSiMS STT-RAM Simulation and Modeling System to assist memory systems researchers. After providing background on the operation of STT-RAM magnetic tunnel junctions (MTJs), we demonstrate how to fit three different published MTJ models to our model and normalize their characteristics with respect to common metrics. The high-speed switching behavior of the designs is evaluated using macromagnetic simulations. We have also added a first-order model for STT-RAM memory arrays to the CACTI memory modeling tool, which we then use to evaluate the performance, energy consumption, and area for: (i) a high-performance cache, (ii) a high-capacity cache, and (iii) a high-density memory.