Enabling architectural innovations using non-volatile memory
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Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM)
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
The STeTSiMS STT-RAM simulation and modeling system
Proceedings of the International Conference on Computer-Aided Design
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems
Proceedings of the International Conference on Computer-Aided Design
Multi retention level STT-RAM cache designs with a dynamic refresh scheme
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
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Optimizing NAND flash-based SSDs via retention relaxation
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Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors
Proceedings of the 49th Annual Design Automation Conference
Write-optimized reliable design of STT MRAM
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
A dual-mode architecture for fast-switching STT-RAM
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Improving energy efficiency of write-asymmetric memories by log style write
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Process variation aware data management for STT-RAM cache design
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
OAP: an obstruction-aware cache management policy for STT-RAM last-level caches
Proceedings of the Conference on Design, Automation and Test in Europe
Cache coherence enabled adaptive refresh for volatile STT-RAM
Proceedings of the Conference on Design, Automation and Test in Europe
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory
Proceedings of the Conference on Design, Automation and Test in Europe
DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes
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Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh
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A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies
ACM Transactions on Architecture and Code Optimization (TACO)
NVM duet: unified working memory and persistent store architecture
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C1C: A configurable, compiler-guided STT-RAM L1 cache
ACM Transactions on Architecture and Code Optimization (TACO)
The Journal of Supercomputing
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Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory technology that is a potential universal memory that could replace SRAM in processor caches. This paper presents a novel approach for redesigning STT-RAM memory cells to reduce the high dynamic energy and slow write latencies. We lower the retention time by reducing the planar area of the cell, thereby reducing the write current, which we then use with CACTI to design caches and memories. We simulate quad-core processor designs using a combination of SRAM- and STT-RAM-based caches. Since ultra-low retention STT-RAM may lose data, we also provide a preliminary evaluation for a simple, DRAMstyle refresh policy. We found that a pure STT-RAM cache hierarchy provides the best energy efficiency, though a hybrid design of SRAM-based L1 caches with reduced-retention STT-RAM L2 and L3 caches eliminates performance loss while still reducing the energy-delay product by more than 70%.