A low-power phase change memory based hybrid cache architecture
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Power and performance of read-write aware hybrid caches with non-volatile memories
Proceedings of the Conference on Design, Automation and Test in Europe
A novel si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
FREE-p: Protecting non-volatile memory against both hard and soft errors
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
Relaxing non-volatility for fast and energy-efficient STT-RAM caches
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
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The emergence of non-volatile memory technologies such as Spin Torque Transfer Magneto-resistive Random Access Memory RAM and Phase Change Memories provide new opportunities for architectural innovations. While the zero off-state leakage, fast read access and high densities of these memories make them attractive options as compared to SRAM, their high write energies and latencies as well as their endurance are a concern. We provide three different architectural techniques that utilize the STT-MRAM characteristics to enable new functionalities. First, we show how exploiting the higher density of STT-MRAM in embedded multi-tasked systems can reduce the context switch overhead. Second, we use the STT-MRAM to create a reliable copy of SRAM structures vulnerable to radiation-induced transient errors to improve reliability. Finally, we show a hybrid cache architecture that uses a mix of emerging TFET technology and STT-MRAM technology. Our results indicate that active leakage is still a concern in STT-MRAM structures.