Enabling architectural innovations using non-volatile memory
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
System implications of memory reliability in exascale computing
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
Preventing PCM banks from seizing too much power
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Pay-As-You-Go: low-overhead hard-error correction for phase change memories
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Exploring latency-power tradeoffs in deep nonvolatile memory hierarchies
Proceedings of the 9th conference on Computing Frontiers
Point and discard: a hard-error-tolerant architecture for non-volatile last level caches
Proceedings of the 49th Annual Design Automation Conference
Age-based PCM wear leveling with nearly zero search cost
Proceedings of the 49th Annual Design Automation Conference
ER: elastic RESET for low power and long endurance MLC based phase change memory
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory
ACM Transactions on Architecture and Code Optimization (TACO)
Using managed runtime systems to tolerate holes in wearable memories
Proceedings of the 34th ACM SIGPLAN conference on Programming language design and implementation
Proceedings of the ACM SIGMETRICS/international conference on Measurement and modeling of computer systems
Phase-change memory: An architectural perspective
ACM Computing Surveys (CSUR)
ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates
Proceedings of the 40th Annual International Symposium on Computer Architecture
Bit mapping for balanced PCM cell programming
Proceedings of the 40th Annual International Symposium on Computer Architecture
Zombie memory: extending memory lifetime by reviving dead blocks
Proceedings of the 40th Annual International Symposium on Computer Architecture
Practical nonvolatile multilevel-cell phase change memory
SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Aegis: partitioning data block for efficient recovery of stuck-at-faults in phase change memory
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
ACM Transactions on Architecture and Code Optimization (TACO)
NVM duet: unified working memory and persistent store architecture
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
Endurance-aware cache line management for non-volatile caches
ACM Transactions on Architecture and Code Optimization (TACO)
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Emerging non-volatile memories such as phase-change RAM (PCRAM) offer significant advantages but suffer from write endurance problems. However, prior solutions are oblivious to soft errors (recently raised as a potential issue even for PCRAM) and are incompatible with high-level fault tolerance techniques such as chipkill. To additionally address such failures requires unnecessarily high costs for techniques that focus singularly on wear-out tolerance. In this paper, we propose fine-grained remapping with ECC and embedded pointers (FREE-p). FREE-p remaps fine-grained worn-out NVRAM blocks without requiring large dedicated storage. We discuss how FREE-p protects against both hard and soft errors and can be extended to chipkill. Further, FREE-p can be implemented purely in the memory controller, avoiding custom NVRAM devices. In addition to these benefits, FREE-p increases NVRAM lifetime by up to 26% over the state-of-the-art even with severe process variation while performance degradation is less than 2% for the initial 7 years.