Adaptive Cache Compression for High-Performance Processors
Proceedings of the 31st annual international symposium on Computer architecture
A durable and energy efficient main memory using phase change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Characterizing and mitigating the impact of process variations on phase change based memory systems
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Use ECP, not ECC, for hard failures in resistive memories
Proceedings of the 37th annual international symposium on Computer architecture
Mercury: A fast and energy-efficient multi-level cell based Phase Change Memory system
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
FREE-p: Protecting non-volatile memory against both hard and soft errors
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscaling
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Energy-efficient multi-level cell phase-change memory system with data encoding
ICCD '11 Proceedings of the 2011 IEEE 29th International Conference on Computer Design
A morphable phase change memory architecture considering frequent zero values
ICCD '11 Proceedings of the 2011 IEEE 29th International Conference on Computer Design
Preventing PCM banks from seizing too much power
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Efficient scrub mechanisms for error-prone emerging memories
HPCA '12 Proceedings of the 2012 IEEE 18th International Symposium on High-Performance Computer Architecture
Improving write operations in MLC phase change memory
HPCA '12 Proceedings of the 2012 IEEE 18th International Symposium on High-Performance Computer Architecture
FTL2: a hybrid flash translation layer with logging for write reduction in flash memory
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Compiler directed write-mode selection for high performance low power volatile PCM
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Tri-level-cell phase change memory: toward an efficient and reliable memory system
Proceedings of the 40th Annual International Symposium on Computer Architecture
Practical nonvolatile multilevel-cell phase change memory
SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
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Phase Change Memory (PCM) has recently emerged as a promising nonvolatile memory technology. To effectively increase memory capacity and reduce per bit fabrication cost, multi-level cell (MLC) PCM stores more than one bit per cell by differentiating multiple intermediate resistance levels. However, MLC PCM suffers from significantly shortened endurance due to its large RESET current that initiates the cell state. In this paper, we propose elastic RESET (ER) to construct non-2n-state MLC PCM, e.g., 3-state MLC PCM instead of 4-state one for 2-bit MLC. We then adopt data compression and propose fraction encoding to store compressed data using non-2n-state MLC. By reducing RESET energy, ER significantly reduces write power and prolongs PCM lifetime. On average, we observed 17% RESET power reduction and 32x endurance improvement for 2-bit MLC.