Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
WCET Centric Data Allocation to Scratchpad Memory
RTSS '05 Proceedings of the 26th IEEE International Real-Time Systems Symposium
Chronos: A timing analyzer for embedded software
Science of Computer Programming
Data cache locking for tight timing calculations
ACM Transactions on Embedded Computing Systems (TECS)
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Phase-change random access memory: a scalable technology
IBM Journal of Research and Development
Minimizing WCET for Real-Time Embedded Systems via Static Instruction Cache Locking
RTAS '09 Proceedings of the 2009 15th IEEE Symposium on Real-Time and Embedded Technology and Applications
Architecting phase change memory as a scalable dram alternative
Proceedings of the 36th annual international symposium on Computer architecture
A durable and energy efficient main memory using phase change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Scalable high performance main memory system using phase-change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Optimal static WCET-aware scratchpad allocation of program code
Proceedings of the 46th Annual Design Automation Conference
Characterizing and mitigating the impact of process variations on phase change based memory systems
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Write activity reduction on flash main memory via smart victim cache
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Improved memory-access analysis for x86 executables
CC'08/ETAPS'08 Proceedings of the Joint European Conferences on Theory and Practice of Software 17th international conference on Compiler construction
Morphable memory system: a robust architecture for exploiting multi-level phase change memories
Proceedings of the 37th annual international symposium on Computer architecture
Demand-based block-level address mapping in large-scale NAND flash storage systems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Minimizing write activities to non-volatile memory via scheduling and recomputation
SASP '10 Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors (SASP)
Mercury: A fast and energy-efficient multi-level cell based Phase Change Memory system
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscaling
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems
Proceedings of the 48th Design Automation Conference
Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory
Proceedings of the 48th Design Automation Conference
Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system
DSN '11 Proceedings of the 2011 IEEE/IFIP 41st International Conference on Dependable Systems&Networks
Preventing PCM banks from seizing too much power
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Efficient scrub mechanisms for error-prone emerging memories
HPCA '12 Proceedings of the 2012 IEEE 18th International Symposium on High-Performance Computer Architecture
Improving write operations in MLC phase change memory
HPCA '12 Proceedings of the 2012 IEEE 18th International Symposium on High-Performance Computer Architecture
The bleak future of NAND flash memory
FAST'12 Proceedings of the 10th USENIX conference on File and Storage Technologies
Write Activity Minimization for Nonvolatile Main Memory Via Scheduling and Recomputation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ER: elastic RESET for low power and long endurance MLC based phase change memory
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
PreSET: improving performance of phase change memories by exploiting asymmetry in write times
Proceedings of the 39th Annual International Symposium on Computer Architecture
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
The design of sustainable wireless sensor network node using solar energy and phase change memory
Proceedings of the Conference on Design, Automation and Test in Europe
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Micro-Controller Units (MCUs) are widely adopted ubiquitous computing devices. Due to tight cost and energy constraints, MCUs often integrate very limited internal RAM memory on top of Flash storage, which exposes Flash to heavy write traffic and results in short system lifetime. Architecting emerging Phase Change Memory (PCM) is a promising approach for MCUs due to its fast read speed and long write endurance. However, PCM, especially multi-level cell (MLC) PCM, has long write latency and requires large write energy, which diminishes the benefits of its replacement of traditional Flash. By studying MLC PCM write operations, we observe that writing MLC PCM can take advantages of two write modes --- fast write leaves cells in volatile state, and slow write leaves cells in non-volatile state. In this paper, we propose a compiler directed dual-write (CDDW) scheme that selects the best write mode for each write operation to maximize the overall performance and energy efficiency. Our experimental results show that CDDW reduces dynamic energy by 32.4%(33.8%) and improves performance by 6.3%(35.9%) compared with an all fast(slow) write approach.