MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
RTAS '99 Proceedings of the Fifth IEEE Real-Time Technology and Applications Symposium
Assigning Program and Data Objects to Scratchpad for Energy Reduction
Proceedings of the conference on Design, automation and test in Europe
Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm Comparison
ECRTS '05 Proceedings of the 17th Euromicro Conference on Real-Time Systems
WCET Centric Data Allocation to Scratchpad Memory
RTSS '05 Proceedings of the 26th IEEE International Real-Time Systems Symposium
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
ECRTS '06 Proceedings of the 18th Euromicro Conference on Real-Time Systems
Fast, Efficient and Predictable Memory Accesses: Optimization Algorithms for Memory Architecture Aware Compilation
WCET-Directed Dynamic Scratchpad Memory Allocation of Data
ECRTS '07 Proceedings of the 19th Euromicro Conference on Real-Time Systems
Compile-time decided instruction cache locking using worst-case execution paths
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Design of a WCET-Aware C Compiler
ESTMED '06 Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia
Advanced Memory Optimization Techniques for Low-Power Embedded Processors
Advanced Memory Optimization Techniques for Low-Power Embedded Processors
Proceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization
A dynamic instruction scratchpad memory for embedded processors managed by hardware
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
Static bus schedule aware scratchpad allocation in multiprocessors
Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
WCET-driven cache-aware code positioning
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
WCET-driven branch prediction aware code positioning
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Software—Practice & Experience
WCET-centric partial instruction cache locking
Proceedings of the 49th Annual Design Automation Conference
WCET-aware data selection and allocation for scratchpad memory
Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems
WCET-aware static locking of instruction caches
Proceedings of the Tenth International Symposium on Code Generation and Optimization
Proceedings of the tenth ACM international conference on Embedded software
Compiler directed write-mode selection for high performance low power volatile PCM
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetching
Proceedings of the 50th Annual Design Automation Conference
Building timing predictable embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
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Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access will result in a definite cache hit or miss. This unpredictability is highly undesired especially when designing real-time systems where the worst-case execution time (WCET) is one of the key metrics. Scratchpad memories (SPMs) have proven to be a fully predictable alternative to caches. In contrast to caches, however, SPMs require dedicated compiler support. This paper presents an optimal static SPM allocation algorithm for program code. It minimizes WCETs by placing the most beneficial parts of a program's code in an SPM. Our results underline the effectiveness of the proposed techniques. For a total of 73 realistic benchmarks, we reduced WCETs on average by 7.4% up to 40%. Additionally, the run times of our ILP-based SPM allocator are negligible.