A superblock-based flash translation layer for NAND flash memory
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
An adaptive two-level management for the flash translation layer in embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications
ACM Transactions on Embedded Computing Systems (TECS)
Deterministic service guarantees for nand flash using partial block cleaning
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Proceedings of the 46th Annual Design Automation Conference
RNFTL: a reuse-aware NAND flash translation layer for flash memory
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
KAST: K-Associative Sector Translation for NAND flash memory in real-time systems
Proceedings of the Conference on Design, Automation and Test in Europe
Demand-based block-level address mapping in large-scale NAND flash storage systems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Meta-Cure: a reliability enhancement strategy for metadata in NAND flash memory storage systems
Proceedings of the 49th Annual Design Automation Conference
An efficient method for record management in flash memory environment
Journal of Systems Architecture: the EUROMICRO Journal
BLog: block-level log-block management for NAND flash memorystorage systems
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Compiler directed write-mode selection for high performance low power volatile PCM
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Cooperating virtual memory and write buffer management for flash-based storage systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3D-FlashMap: a physical-location-aware block mapping strategy for 3D NAND flash memory
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Modern flash technologies: a flash translation layer perspective
International Journal of High Performance Systems Architecture
A survey of address translation technologies for flash memories
ACM Computing Surveys (CSUR)
The harey tortoise: managing heterogeneous write performance in SSDs
USENIX ATC'13 Proceedings of the 2013 USENIX conference on Annual Technical Conference
DHeating: dispersed heating repair for self-healing NAND flash memory
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Adaptive range-based address mapping for the flash storage devices with explosive capacity
Proceedings of the 8th International Conference on Ubiquitous Information Management and Communication
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The new write constraints of multi-level cell (MLC) NAND flash memory make most of the existing flash translation layer (FTL) schemes inefficient or inapplicable. In this paper, we solve several fundamental problems in the design of MLC flash translation layer. The objective is to reduce the garbage collection overhead so as to reduce the average system response time. We make the key observation that the valid page copy is the essential garbage collection overhead. Based on this observation, we propose two approaches, namely, concentrated mapping and postponed reclamation, to effective reduce the valid page copies. We conduct experiments on a set of benchmarks from both the real world and synthetic traces. The experimental results show that our scheme can achieve a significant reduction in the average system response time compared with the previous work.