BPLRU: a buffer management scheme for improving random writes in flash storage
FAST'08 Proceedings of the 6th USENIX Conference on File and Storage Technologies
Improving NAND Flash Based Disk Caches
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Design tradeoffs for SSD performance
ATC'08 USENIX 2008 Annual Technical Conference on Annual Technical Conference
Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Characterizing flash memory: anomalies, observations, and applications
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Exploiting Internal Parallelism of Flash-based SSDs
IEEE Computer Architecture Letters
KAST: K-Associative Sector Translation for NAND flash memory in real-time systems
Proceedings of the Conference on Design, Automation and Test in Europe
FAST'11 Proceedings of the 9th USENIX conference on File and stroage technologies
Reliably erasing data from flash-based solid state drives
FAST'11 Proceedings of the 9th USENIX conference on File and stroage technologies
ROSE: A Novel Flash Translation Layer for NAND Flash Memory Based on Hybrid Address Translation
IEEE Transactions on Computers
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems
Proceedings of the 48th Design Automation Conference
WAFTL: A workload adaptive flash translation layer with data partition
MSST '11 Proceedings of the 2011 IEEE 27th Symposium on Mass Storage Systems and Technologies
The bleak future of NAND flash memory
FAST'12 Proceedings of the 10th USENIX conference on File and Storage Technologies
Design and analysis of flash translation layers for multi-channel NAND flash-based storage devices
IEEE Transactions on Consumer Electronics
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Recent years have witnessed significant gains in the adoption of flash technology due to increases in bit density, enabling higher capacities and lower prices. Unfortunately, these improvements come at a significant cost to performance with trends pointing toward worst-case flash program latencies on par with disk writes. We extend a conventional flash translation layer to schedule flash program operations to flash pages based on the operations' performance needs and the pages' performance characteristics. We then develop policies to improve performance in two scenarios: First, we improve peak performance for latency-critical operations of short bursts of intensive activity by 36%. Second, we realize steady-state bandwidth improvements of up to 95% by rate-matching garbage collection performance and external access performance.