An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems
RTAS '02 Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02)
A superblock-based flash translation layer for NAND flash memory
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
An adaptive two-level management for the flash translation layer in embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
Endurance enhancement of flash-memory storage systems: an efficient static wear leveling design
Proceedings of the 44th annual Design Automation Conference
A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications
ACM Transactions on Embedded Computing Systems (TECS)
Design tradeoffs for SSD performance
ATC'08 USENIX 2008 Annual Technical Conference on Annual Technical Conference
LAST: locality-aware sector translation for NAND flash memory-based storage systems
ACM SIGOPS Operating Systems Review
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Proceedings of the 46th Annual Design Automation Conference
CFTL: a convertible flash translation layer adaptive to data access patterns
Proceedings of the ACM SIGMETRICS international conference on Measurement and modeling of computer systems
KAST: K-Associative Sector Translation for NAND flash memory in real-time systems
Proceedings of the Conference on Design, Automation and Test in Europe
LazyFTL: a page-level flash translation layer optimized for NAND flash memory
Proceedings of the 2011 ACM SIGMOD International Conference on Management of data
MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems
Proceedings of the 48th Design Automation Conference
Rejuvenator: A static wear leveling algorithm for NAND flash memory with minimized overhead
MSST '11 Proceedings of the 2011 IEEE 27th Symposium on Mass Storage Systems and Technologies
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
ACM Transactions on Embedded Computing Systems (TECS)
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Due to the fast-growing amount of data in mobile applications and big data applications, there is a strong demand for the capacity of flash storage devices. Due to the fast-growing capacity, flash storage devices face a serious challenge on reducing their RAM space consumption for the address mapping information without sacrificing device performance. In contrast to the existing table-based address mapping designs, we propose an adaptive range-based address mapping scheme whose RAM space requirement is minimized and independent of the storage capacity. In this scheme, an unbalanced range-based binary search tree with an efficient space allocator and garbage collection policy is designed to minimize the RAM space for the address mapping information with optimized performance to search for the address mapping information. Some evaluations were conducted to evaluate the capability of the proposed scheme, and the results are encouraging.