A reliability enhancement design under the flash translation layer for MLC-based flash-memory storage systems

  • Authors:

  • Yuan-Hao Chang;Ming-Chang Yang;Tei-Wei Kuo;Ren-Hung Hwang

  • Affiliations:

  • Academia Sinica, Taiwan, Republic of China;National Taiwan University, Taiwan, Republic of China;National Taiwan University, Taiwan, Republic of China;National Chung-Cheng University, Taiwan, Republic of China

  • Venue:
  • ACM Transactions on Embedded Computing Systems (TECS)
  • Year:
  • 2013

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Abstract

Although flash memory has gained very strong momentum in the storage market, the reliability of flash-memory chips has been dropped significantly in the past years. This article presents a reliability enhancement design under the flash management layer (i.e., flash translation layer) to address this concern so as to reduce the design complexity of flash-memory management software/firmware and to improve the maintainability and portability of existing and future products. In particular, a log-based write strategy with a hash-based caching policy is proposed to provide extra ECC redundancy and performance improvement. Strategies for bad block management are also presented. The failure rate of flash-memory storage systems is analyzed with the considerations of bit errors. The proposed design is later evaluated by a series of experiments based on realistic traces. It was shown that the proposed approach could significantly improve the reliability of flash memory with very limited system overheads.