A cost-aware page replacement algorithm for NAND flash based mobile embedded systems
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Efficient cache design for solid-state drives
Proceedings of the 7th ACM international conference on Computing frontiers
Demand-based block-level address mapping in large-scale NAND flash storage systems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A hybrid flash translation layer with adaptive merge for SSDs
ACM Transactions on Storage (TOS)
A driver-layer caching policy for removable storage devices
ACM Transactions on Storage (TOS)
CAVE: channel-aware buffer management scheme for solid state disk
Proceedings of the 2011 ACM Symposium on Applied Computing
Plugging versus logging: a new approach to write buffer management for solid-state disks
Proceedings of the 48th Design Automation Conference
ExLRU: a unified write buffer cache management for flash memory
EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software
MEDI'11 Proceedings of the First international conference on Model and data engineering
Reorder the write sequence by virtual write buffer to extend SSD's lifespan
NPC'11 Proceedings of the 8th IFIP international conference on Network and parallel computing
An adaptive write buffer management scheme for flash-based SSDs
ACM Transactions on Storage (TOS)
A caching-oriented management design for the performance enhancement of solid-state drives
ACM Transactions on Storage (TOS)
Delta-FTL: improving SSD lifetime via exploiting content locality
Proceedings of the 7th ACM european conference on Computer Systems
Reducing SSD read latency via NAND flash program and erase suspension
FAST'12 Proceedings of the 10th USENIX conference on File and Storage Technologies
h-Buffer: an adaptive buffer management scheme for flash-based storage devices
DASFAA'12 Proceedings of the 17th international conference on Database Systems for Advanced Applications
A dual-grained FTL for flash memory
DASFAA'12 Proceedings of the 17th international conference on Database Systems for Advanced Applications
Working-set-based address mapping for ultra-large-scaled flash devices
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
TreeFTL: efficient RAM management for high performance of NAND flash-based storage systems
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting workload dynamics to improve SSD read latency via differentiated error correction codes
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Cooperating virtual memory and write buffer management for flash-based storage systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
BLAS: Block-level adaptive striping for solid-state drives
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Surviving sensor node failures by MMU-less incremental checkpointing
Journal of Systems and Software
Migration-based hybrid cache design for file systems over flash storage devices
ACM SIGAPP Applied Computing Review
Hi-index | 14.98 |
While NAND flash memory is used in a variety of end-user devices, it has a few disadvantages, such as asymmetric speed of read and write operations, inability to in-place updates, among others. To overcome these problems, various flash-aware strategies have been suggested in terms of buffer cache, file system, FTL, and others. Also, the recent development of next-generation nonvolatile memory types such as MRAM, FeRAM, and PRAM provide higher commercial value to Non-Volatile RAM (NVRAM). At today's prices, however, they are not yet cost-effective. In this paper, we suggest the utilization of small-sized, next-generation NVRAM as a write buffer to improve the overall performance of NAND flash memory-based storage systems. We propose various block-based NVRAM write buffer management policies and evaluate the performance improvement of NAND flash memory-based storage systems under each policy. Also, we propose a novel write buffer-aware flash translation layer algorithm, optimistic FTL, which is designed to harmonize well with NVRAM write buffers. Simulation results show that the proposed buffer management policies outperform the traditional page-based LRU algorithm and the proposed optimistic FTL outperforms previous log block-based FTL algorithms, such as BAST and FAST.