An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems
RTAS '02 Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02)
A multi-channel architecture for high-performance NAND flash-based storage system
Journal of Systems Architecture: the EUROMICRO Journal
A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications
ACM Transactions on Embedded Computing Systems (TECS)
Design tradeoffs for SSD performance
ATC'08 USENIX 2008 Annual Technical Conference on Annual Technical Conference
μ-FTL:: a memory-efficient flash translation layer supporting multiple mapping granularities
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
LAST: locality-aware sector translation for NAND flash memory-based storage systems
ACM SIGOPS Operating Systems Review
Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
FTL design exploration in reconfigurable high-performance SSD for server applications
Proceedings of the 23rd international conference on Supercomputing
Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices
IEEE Transactions on Computers
Superblock FTL: A superblock-based flash translation layer with a hybrid address translation scheme
ACM Transactions on Embedded Computing Systems (TECS)
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
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The Flash Translation Layer (FTL) in Solid-State Disks (SSDs) maps logical addresses to physical addresses for disk drive virtualization. In order to reduce garbage collection overhead, we propose full associative striped block-level mapping. In addition, an adaptive merge is proposed to avoid excessive data block reconstructions during garbage collection. With these mechanisms, the write latency is improved up to 78% in comparison with the previous multichannel hybrid FTLs in a sample PC trace. The performance improvements stem from 52% reduced garbage collection.