Using data clustering to improve cleaning performance for plash memory
Software—Practice & Experience
Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems
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Real-time garbage collection for flash-memory storage systems of real-time embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
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Efficient management for large-scale flash-memory storage systems with resource conservation
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IEEE Transactions on Computers
A superblock-based flash translation layer for NAND flash memory
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Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2007 ACM symposium on Applied computing
A Re-configurable FTL (Flash Translation Layer) Architecture for NAND Flash based Applications
RSP '07 Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping
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TCON'95 Proceedings of the USENIX 1995 Technical Conference Proceedings
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OSDI '94 Proceedings of the 1st USENIX conference on Operating Systems Design and Implementation
A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
A group-based wear-leveling algorithm for large-capacity flash memory storage systems
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications
ACM Transactions on Embedded Computing Systems (TECS)
Deterministic service guarantees for nand flash using partial block cleaning
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
Distribution log buffer scheme for NAND flash memory
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A hybrid flash translation layer with adaptive merge for SSDs
ACM Transactions on Storage (TOS)
LSTAFF*: an efficient flash translation layer for large block flash memory
Proceedings of the 2011 ACM Symposium on Applied Computing
MFTL: A Design and Implementation for MLC Flash Memory Storage Systems
ACM Transactions on Storage (TOS)
Hot-LSNs distributing wear-leveling algorithm for flash memory
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Dual greedy: adaptive garbage collection for page-mapping solid-state disks
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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HotStorage'13 Proceedings of the 5th USENIX conference on Hot Topics in Storage and File Systems
ACM Transactions on Storage (TOS)
BLAS: Block-level adaptive striping for solid-state drives
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Random data-aware flash translation layer for NAND flash-based smart devices
The Journal of Supercomputing
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In NAND flash-based storage systems, an intermediate software layer called a Flash Translation Layer (FTL) is usually employed to hide the erase-before-write characteristics of NAND flash memory. We propose a novel superblock-based FTL scheme, which combines a set of adjacent logical blocks into a superblock. In the proposed Superblock FTL, superblocks are mapped at coarse granularity, while pages inside the superblock are mapped freely at fine granularity to any location in several physical blocks. To reduce extra storage and flash memory operations, the fine-grain mapping information is stored in the spare area of NAND flash memory. This hybrid address translation scheme has the flexibility provided by fine-grain address translation, while reducing the memory overhead to the level of coarse-grain address translation. Our experimental results show that the proposed FTL scheme significantly outperforms previous block-mapped FTL schemes with roughly the same memory overhead.