Algorithms and data structures for flash memories
ACM Computing Surveys (CSUR)
A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
STAFF: A flash driver algorithm minimizing block erasures
Journal of Systems Architecture: the EUROMICRO Journal
Swap-Aware Garbage Collection for NAND Flash Memory Based Embedded Systems
CIT '07 Proceedings of the 7th IEEE International Conference on Computer and Information Technology
A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications
ACM Transactions on Embedded Computing Systems (TECS)
LAST: locality-aware sector translation for NAND flash memory-based storage systems
ACM SIGOPS Operating Systems Review
An adaptive block-set based management for large-scale flash memory
Proceedings of the 2009 ACM symposium on Applied Computing
Improving Flash Wear-Leveling by Proactively Moving Static Data
IEEE Transactions on Computers
Superblock FTL: A superblock-based flash translation layer with a hybrid address translation scheme
ACM Transactions on Embedded Computing Systems (TECS)
IEEE Transactions on Computers
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
A Flash Translation Layer for nand Flash-Based Multimedia Storage Devices
IEEE Transactions on Multimedia
Hot-LSNs distributing wear-leveling algorithm for flash memory
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
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The design of flash memory systems for smart devices differs significantly from traditional storage systems, because most updates involve the random data. A previously proposed algorithm known as Switchable Address Translation (SAT) enhances the performance of multimedia storage devices; however, it exhibits low space utilization and executes intense monitoring. In this paper, we propose the Random Data-Aware Flash Translation Layer (RDA), which enhances the performance and durability of smart devices. RDA improves low space utilization using the state transition. Furthermore, RDA prolongs the durability of the flash memory by spreading out the random data. According to our experiment results, RDA reduces the total number of erase operations and narrows the deviation of erase operations between the physical blocks, when compared to SAT.