Cleaning policies in mobile computers using flash memory
Journal of Systems and Software
On efficient wear leveling for large-scale flash-memory storage systems
Proceedings of the 2007 ACM symposium on Applied computing
A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
A group-based wear-leveling algorithm for large-capacity flash memory storage systems
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
STAFF: A flash driver algorithm minimizing block erasures
Journal of Systems Architecture: the EUROMICRO Journal
Swap-Aware Garbage Collection for NAND Flash Memory Based Embedded Systems
CIT '07 Proceedings of the 7th IEEE International Conference on Computer and Information Technology
A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications
ACM Transactions on Embedded Computing Systems (TECS)
Mechanising a formal model of flash memory
Science of Computer Programming
An adaptive block-set based management for large-scale flash memory
Proceedings of the 2009 ACM symposium on Applied Computing
A survey of Flash Translation Layer
Journal of Systems Architecture: the EUROMICRO Journal
Improving Flash Wear-Leveling by Proactively Moving Static Data
IEEE Transactions on Computers
Superblock FTL: A superblock-based flash translation layer with a hybrid address translation scheme
ACM Transactions on Embedded Computing Systems (TECS)
Response time distribution of flash memory accesses
Performance Evaluation
A Hybrid Approach to NAND-Flash-Based Solid-State Disks
IEEE Transactions on Computers
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
An efficient and advanced space-management technique for flash memory using reallocation blocks
IEEE Transactions on Consumer Electronics
Random data-aware flash translation layer for NAND flash-based smart devices
The Journal of Supercomputing
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Flash memory offers attractive features, such as non-volatile, shock resistance, fast access and low power consumption for data storage. However, it has one main drawback of requiring an erase before updating the contents. Furthermore, the flash memory can only be erased for a limited number of times. These characteristics are controlled by a software layer called the flash translation layer (FTL). FTL efficiently manages read, write, and erase operations to enhance the overall performance, and considers wear-leveling to prolong the durability of flash memory. In this article, we identify the logical sector numbers corresponding to random data, termed as hot-LSNs, and distribute them to all available blocks without degrading the performance of the flash memory. From our evaluation, we found that the extra erase operations for distributing the hot-LSNs are very low compared to the overall performance. Even though Hot-LSNs Distributing Wear-Leveling Algorithm (Hot-DL) incorporates wear-leveling in the performance enhancing algorithm, Hot-DL only requires approximately 0.015% of extra erase operations compared to previous well-optimized performance enhancing algorithms, shared buffer scheme.