An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems
RTAS '02 Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02)
An Efficient NAND Flash File System for Flash Memory Storage
IEEE Transactions on Computers
ACM Transactions on Storage (TOS)
File system design for an NFS file server appliance
WTEC'94 Proceedings of the USENIX Winter 1994 Technical Conference on USENIX Winter 1994 Technical Conference
Formalising Flash Memory: First Steps
ICECCS '07 Proceedings of the 12th IEEE International Conference on Engineering Complex Computer Systems
Endurance enhancement of flash-memory storage systems: an efficient static wear leveling design
Proceedings of the 44th annual Design Automation Conference
An approximate compositional approach to the analysis of fluid queue networks
Performance Evaluation
Proceedings of the 2008 ACM symposium on Applied computing
BPLRU: a buffer management scheme for improving random writes in flash storage
FAST'08 Proceedings of the 6th USENIX Conference on File and Storage Technologies
A Reliability Enhancing Mechanism for a Large Flash Embedded Satellite Storage System
ICONS '08 Proceedings of the Third International Conference on Systems
Mechanising a formal model of flash memory
Science of Computer Programming
Response time distribution of flash memory accesses
Proceedings of the 3rd International Conference on Performance Evaluation Methodologies and Tools
Storage workload modelling by hidden Markov models: Application to Flash memory
Performance Evaluation
Performance implications of flash and storage class memories
Proceedings of the 12th ACM SIGMETRICS/PERFORMANCE joint international conference on Measurement and Modeling of Computer Systems
Hot-LSNs distributing wear-leveling algorithm for flash memory
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
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Flash memory is becoming an increasingly important storage component among non-volatile storage devices. Its cost is decreasing dramatically and its performance continues to improve, which makes it a serious competitor for disks and a candidate for enterprise-tier storage devices of the future. Consequently, it is important to devise models and tools to analyse its behaviour and to evaluate its effects on a system's performance. We propose a Markov modulated fluid model with priority classes to investigate the response time characteristics of Flash memory accesses. This model can represent well the Flash access operation types, respecting the erase/write/read relative priorities and autocorrelations. We apply the model to estimate response time densities at the chip for an OLTP-type of workload and indicate the magnitude of the penalty suffered by writes under priority scheduling of read operations. The model is validated against a customised hardware simulator that uses input-traces typical of our Markovian workload description.